1. Field of the Invention
This invention relates to a semiconductor integrated capable of increasing drive performance by changing a substrate potential of a MOS transistor (back gate voltage) when a MOS transistor is employed as an output transistor of a voltage converter such as a voltage regulator (referred to herein as a V/R circuit) in an integrated circuit, a charge pump circuit (hereinafter referred to as CP circuit), or a switching element (hereinafter referred to as SW element) of a switching regulator.
2. Description of Related Art
Voltage regulators outputting a related positive voltage such as shown in the circuit diagram of FIG. 9 are well-known. Namely, a related voltage regulator comprises a voltage regulator control circuit consisting of an error amplifier 13 for amplifying a difference voltage for a reference voltage Vref of a reference voltage circuit 10 and a voltage of a connection point of bleeder resistors 11, 12 dividing a voltage Vout (referred to as output voltage in the following) of a voltage regulator output terminal 5, and an output transistor 14. A positive power supply voltage VDD is applied to a power supply voltage terminal 15.
If an output voltage of the error amplifier 13 is taken to be Verr, an output voltage of the reference voltage circuit 10 is taken to be Vref, and a voltage of a connection point of the bleeder resistors 11, 12 is taken to be Va, then, if Vref greater than Va, Verr becomes low, while conversely, if Vref less than Va, then Verr becomes high.
The output transistor 14 is a p-channel MOS transistor in this case. Therefore, when Verr becomes low, the voltage across the gate and source becomes large, the on resistance becomes small and operation is such that the output voltage Vout is caused to rise. Conversely, when Verr goes high, operation is such that the on resistance of the output transistor 14 goes high, and the output voltage goes low, so that the output voltage Vout is kept at a fixed value.
An ON resistance Ron of the output transistor 14 constitutes a function for the voltage Vgs between the gate and source and a transistor threshold voltage Vt, with the ON resistance of the transistor being smaller for a larger Vgs-Vt. Typically, the ON resistance for the region where the voltage across the drain and source of the transistor is small is given by equation (1).                     Ron        =                  1                      μ            ·            Cox            ·                          W              /              L                        ·                          (                              Vgs                -                Vt                            )                                                          (        1        )            
Here, xcexc is mobility, Cox is gate capacitance per unit surface area, W is transistor gate width, and L is gate length.
It is necessary to increase the gate width W of the transistor in order to lower the ON resistance of the output transistor. This increases the surface area of the IC and therefore causes costs to increase.
On the other hand, voltage regulators of the related art outputting a negative voltage, such as shown in the circuit diagram of FIG. 10, are well-known. Namely, a related voltage regulator comprises a voltage regulator control circuit consisting of an error amplifier 13 for amplifying a difference voltage for a reference voltage of a reference voltage circuit 10 and a voltage of a connection point of bleeder resistors 11, 12 dividing a voltage xe2x88x92Vout of a voltage regulator output terminal 5, and an output transistor 17. A negative power supply voltage xe2x88x92VSS is applied to a power supply voltage terminal 16. If an output voltage of the error amplifier 13 is taken to be xe2x88x92Verr, an output voltage of the reference voltage circuit 10 is taken to be xe2x88x92Vref, and a voltage of a connection point of the bleeder resistors 11, 12 is taken to be xe2x88x92Va, then, if xe2x88x92Vref less than xe2x88x92Va, xe2x88x92Verr becomes low (approaches xe2x88x92VSS), while conversely, if xe2x88x92Vref greater than xe2x88x92Va, then xe2x88x92Verr becomes high (approaches GND).
An output transistor 17 is an N-channel MOS transistor in this case. Therefore, when xe2x88x92Verr becomes high, the voltage across the gate and source becomes large, the ON resistance becomes small and operation is such that the output voltage Vout is caused to fall. Conversely, when xe2x88x92Verr goes low, operation is such that the ON resistance of the output transistor 17 goes high, and the output voltage goes high, so that the output voltage Vout is kept at a fixed value.
As with the positive voltage regulator, it is necessary to increase the gate width W of the output transistor in order to lower the on resistance of the output transistor, with the on resistance of the output transistor being given by equation (1). This increases the surface area of the IC and therefore causes costs to increase.
A configuration for a circuit taken as a related booster-type SW regulator is shown in FIG. 11.
An input power supply 120 is connected to a coil 121 and a power supply terminal 101 of an SW regulator control circuit 130. The other end of the coil 121 is connected to a drain of an SW element 122 and an anode of a commutation diode 123. A cathode of the diode 123 is connected to an output voltage terminal 102 of the SW regulator, and a capacitor 124 and a load 125 are connected to the output voltage terminal 102. If a voltage of an output voltage terminal 102 is taken to be Vout, the SW regulator control circuit 130 controls the SW element 122 to be on or off in such a manner that Vout is fixed. The gate of the SW terminal 122 is connected to the terminal 103 of the drive circuit 131 of the SW element, and the SW element 122 is made to go on and off as a result of being driven by the voltage Vext of the terminal 103. In FIG. 11, the SW element 122 is an N-channel MOS transistor. The voltage Vext of the output terminal 103 of the drive circuit 131 is outputted as a positive voltage xe2x80x9cHxe2x80x9d in order to put the SW element 122 on, and is outputted as a GND level voltage in order to put the SW element 122 off. The source and substrate of the SW element 122 are both connected to GND.
Generally, it is preferable for the electrical power conversion efficiency of the SW regulator circuit to be high. It is necessary for the electrical power conversion efficiency to be high in order to reduce loss due to on resistance when the SW element 122 is on. If current flowing in the SW element 122 is taken to be I, and on resistance of the SW element is taken to be Ron, then loss Pron when the SW element 122 is on is given by:
Pron=IxIxRonxe2x80x83xe2x80x83(2) 
i.e., it is necessary to lower the on resistance of the SW element in order to make the loss Pron of the SW element small. Typically, the on resistance for the region where the voltage across the drain and source of the MOS transistor is small is given by equation (1) described previously.
It is necessary to increase the gate width W of the transistor in order to lower the on resistance of the MOS transistor. This increases the surface area of the IC and therefore causes costs to increase. Making the gate width W large also increases the capacitance of the gate of the MOS transistor so that loss when charging and discharging the gate capacitance of the MOS transistor when turning the MOS transistor on and off is also increased. The surface area of the drive circuit itself also increases in order to drive this large capacitance.
The configuration of a circuit shown in FIG. 12 is given as an example of a related double-boosting-type circuit. The positive side of a power supply 220 of tie input of FIG. 12 is connected to switch elements 221 and 224, and the negative side of the power supply 220 is connected to the SW terminal 222. A capacitor 225 and SW element 223 are connected to the other end of the SW element 221, with a SW element 224 being connected to the other end of the capacitor 225. A capacitor 226 and load 227 are connected to the other end of the SW element 223. The switch elements 221 to 224 are controlled to go on and off by a signal from a CP control circuit 228.
The switch elements 221 and 222, and 223 and 224 go on and off in a complementary manner. i.e. when switch elements 221 and 222 are on, switch elements 223 and 224 are off, and when switch elements 223 and 224 are on, switch elements 221 and 222 are off. These switch elements then repeatedly go on and off in an alternate manner. Initially, when the switch elements 221 and 222 are on for a sufficiently long time, a voltage the same as the voltage of the power supply 220 is stored at the capacitor 225. If the voltage of the power supply 220 is taken to be VDD, then the voltage VDD is stored at the capacitor 225.
Next, when the SW elements 221 and 222 are turned off and the SW elements 223 and 224 are put on, the voltage of the capacitor 225 on the side of the SW element 224 becomes the voltage of the power supply 220, i.e. VDD, and the charge of the capacitor 225 is stored. The voltage of the SW element 223 for the voltage of the capacitor 225 then becomes 2xc3x97VDD. This voltage is held at the capacitor 226 and is supplied to the load 227.
The turning on and off of the SW element is generally carried out at a frequency in the order of a number of kHz to a number of Mhz. Ideally, it is preferable for the SW elements to have an on resistance of Oxcexa9 and to charge and discharge electrical charge of the capacitance instantaneously. However, in reality, charging and discharging is carried out based on the time constants of the capacitors and the SW elements due to the on resistance of the switch elements.
Loss is also generated during the charging and discharging of the SW elements due to the resistance components of the SW elements.
Generally, it is preferable for the electrical power conversion efficiency of the CP circuit to be high. It is necessary for the electrical power conversion efficiency to be high in order to reduce loss due to ON resistance when the SW elements 221 to 224 are on. If current flowing in the SW element is taken to be I, and on resistance of the SW element is taken to be Ron, then it is necessary to lower the on resistance of the SW element in order to make the loss Pron of the SW element smaller, as can be given by the aforementioned equation (2).
An example where SW elements 222 and 224 are configured from an N-channel MOS transistor and a P-channel MOS transistor is shown in FIG. 13. Numeral 230 in FIG. 13 is an N-channel MOS transistor playing the role of the SW element 222 of FIG. 12, and numeral 231 is a PMOS transistor, playing the role of the SW element 224 of FIG. 12. In FIG. 13, the source and substrate of the P-channel MOS transistor 231 are connected to the positive power supply VDD. On the other hand, the source of the N-channel MOS transistor 230 and the substrate are connected to the negative power supply GND.
When the SW elements are made using MOS transistors, the on resistance for the region of the MOS transistor where the voltage across the drain and source is small and is given by equation (1) as described above.
It is necessary to increase the gate width W of the transistor in order to lower the on resistance of the switch elements made form MOS transistors. This increases the surface area of the IC and therefore causes costs to increase. Making the gate width W large also increases the capacitance of the gate of the MOS transistor so that loss when charging and discharging the gate capacitance of the MOS transistor when turning the MOS transistor on and off is also increased. The surface area of the drive circuit itself also increases in order to drive this large capacitance.
However, with semiconductor integrated circuits of the related art, it is necessary to increase the surface area of the MOS transistors in order to lower on resistance of the output transistors or SW element, with this increasing the cost of the IC circuits.
In order to resolve the problems encountered in the related art, the object of the present invention is to lower MOS transistor ON resistance while suppressing increases in the surface area of MOS transistors of switching elements.